putting it all together

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I am not able to compile my design with the pci_slave included. It keeps looking for a file called pci_slave.vhd. I have downloaded all the files and included the USE work.pci.all; to the top.

What is the proper way of instantiating the component?

Do I need to declare with a "component" definition or just use a port map statement or what?

-- Dan Christidis (christi@ecf.toronto.edu), March 14, 1999


Just to put in my 2 cents worth...

It has been my experience that compiling pci_slave.tdf is not necessary. When I tested the slave design files at home, I put the five files that we have given you with my solution (which consists of two .vhd files) in a directory. When I set the project to the toplevel .vhd file everything compiled just fine.

When I tried the same thing on the sparc machines I got the funky "WORK library" error that Steve Kushnir asked about in another message. This error seems to appear when the .dls files have been corrupted. Compiling the pci_pack.vhd file will regenerate the .dls files and seems to fix the problem.

-- Steven Caranci (caranci@eecg.toronto.edu), March 15, 1999.

Using subdesigns in VHDL requires a little work on your part. (It shouldn't, but that is VHDL.)

To use the PCI_Slave design, *first* you have to compile it independently. Select the pci_slave.tdf as your project and compile it. Now when you change to your main top-level design as the project and compile, it be 'aware' of the subdesign. (Just copying the files into the directory isn't enough.)

Note that since this is declared as a package, you *don't* need a COMPONENT declartion. In the BEGIN/END block of your ARCHITECTURE, you can just instantiate it:

pci_dev : PCI_SLAVE port map (.....);


-- Robin Grindley (grindley@eecg.toronto.edu), March 14, 1999.

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