Not enough room on FPGA?greenspun.com : LUSENET : ece342 : One Thread
When I try to compile my lab #4 (DMA) code, I get the following error during the 'Fitting' phase:
Error: Logic cell requires too many [17/16] shreable expanders Error: No fit found, generating Report File
What are shareable expanders, and how can I reduce the use of them?
Note: When I select another device, Flex 10K, the code compiles and fits fine.
-- Stan Sokorac (firstname.lastname@example.org), February 20, 1999
You have some logic that is too complex for the compiler to fit into the MAX device. It sounds like there are too many or terms in a logic equation. (Note that this equation may be synthesized by the compiler from your state machine flow.)
The report file should contain all of the synthesized equations, and from there you should be able to see what is causing the problem.
There are also a number of options in the fitter that might help, but is difficult to recommend specific options without knowing exactly what the problem is and what the current settings are.
-- Steven Caranci (email@example.com), February 22, 1999.
You can fit the entire design comfortably into the MAX device, but if you do things in even a slightly awkward way you can find the logic synthesis will blow up the complexity immensely. The first step is to try figuring out better/simpler ways of implementing your logic.
Note however that if push comes to shove you *can* use the 10K device on the Altera board. You have all the pin-outs for the connector, just make sure that you change the pin assignments. And when programming make sure that you change the jumpers.
-- Robin Grindley (firstname.lastname@example.org), February 23, 1999.