DMA : LUSENET : ece342 : One Thread

Block diagram is confusing:

Are the arrows correct?

What I don't understand is what exactly triggers the DMA process. Is it the correct address recognized by some decoder (like lab 2)? In that case, when does the DMA process begin. Do we

1. take in the address, data (in write mode), /RW, burst mode(???where is it???), and then

2. assert /BR and wait for /BG and go on with /BGACK ?


1. take control of the bus first?

Thanx, Ben.

-- Ben (, February 17, 1999


The answer to this question might answer your question.

-- Steven Caranci (, February 18, 1999.

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