Lab 3 Wiring problem : LUSENET : ece342 : One Thread

Hi... I was reading the Lab 3 assignment, and I noticed that there are a LOT of wires to hook up to the Altera board:

68000 Address Lines: 23 68000 Data Lines: 8 (Assuming we can leave the high byte unattached) AS, UDS, LDS, RW, DTACK: 5

Address Lines to DRAM: 9 DRAM Data Lines: 8 CAS, RAS, OE, WE to DRAM: 4 -- 57

I would point out that the MAX7128 header has only 42 usable pins (15-56). The FLEX10K has only one usable header as well... the other two are unattached. Is there something I'm missing here? How do we wire all this up to the chip?

Steven Truelove

-- Steven Truelove (, January 28, 1999


Note that the suggested block diagram does not have the data lines going to the DRAM controller.

This leaves:

68k address:  23
68k control:   5
DRAM address:  9
DRAM control:  4
TOTAL:        41

Also, the header from the Altera board only has 42 I/O pins, but also has 3 Input pins: header pins 12, 13, and 14 are pins 1, 84, and 2 (repectively) on the max7128 device. This information is given in Table 1 of the general lab info handout available on the web page.

-- Steven Caranci (, January 29, 1999.

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